1. Technical Field
The present invention relates in general to processors in data processing systems and in particular to the architecture of instruction sets and registers in such processors. Still more particularly, the present invention relates to an instruction set architecture and register architecture in a processor which allows registers to be dynamically typed.
2. Description of the Related Art
Processors in data processing systems include a number of registers used to store operands for the instructions executed by the processor. Typically this includes registers dedicated for use in execution of a particular type of instruction, such as floating point registers. A block diagram of a conventional processor architecture is depicted in FIG. 1. Processor 100 includes a bus interface unit 102 which controls the flow of data between processor 100 and the remainder of the data processing system (not shown). Bus interface unit 102 is connected to both a data cache 104 and an instruction cache 106. Instruction cache 106 supplies instructions to branch unit 108, which determines what sequence of instructions is appropriate given the contents of general purpose registers (GPRs) 110 and floating point registers (FPRs) 112 in processor 100, the availability of load/store unit 114, fixed point execution unit 116, and floating point execution unit 118, and the nature of the instructions themselves. Branch unit 108 forwards the ordered instructions to dispatch unit 120, which issues the individual instructions to the appropriate execution or function unit (load/store unit 114, fixed point execution unit 116, or floating point execution unit 118). point execution unit 116 reads data from general purpose registers 110, while floating point execution unit 118 reads data from floating point registers 112. Load/store unit 114 reads data from general purpose registers 110 or floating point registers 112 and writes data to data cache 104 or to an external memory (not shown) depending on the memory hierarchy and caching protocol employed by the data processing system. Load/store unit 114 also reads data from data cache 104 and writes the data to general purpose registers 110 and floating point registers 112.
Use of separate register types in processors represents a trade-off, dedicating processor area to improve performance of specific operations within the processor. While there are advantages to employing registers of a specific type associated with a function unit operating predominately on operands of that type, static dedication of such registers precludes flexibility which would allow dynamic allocating of registers based on anticipated need. When registers of a particular type are implemented as fast registers close to the associated execution unit, static definition of register type also either requires that a sufficient number of registers be implemented to satisfy the greatest projected demand or degrades performance as a result of "register bottleneck." Registers which are statically defined and shared by multiple execution units of different types requires both that values in such registers be bussed across large distances in the processor and that large numbers of ports be provided for each register. Sharing of register types by different types of execution units complicates register dependency problems and scheduling of instructions for parallel execution.
Static register types also preclude extension of instruction sets, preventing accommodation of new functions and data types after the initial instruction set for the processor has been defined. The instruction sets used in conjunction with static register types typically do not include generic instructions for converting a register value from one data type to another. The processor architectures typically require that converted values be transferred to memory before loading them into new registers. Utilizing static register types and shared registers creates difficulties in saving and restoring register values at subroutine call boundaries and at context switch points.
It would be advantageous, therefore, to permit a compiler to dynamically allocate registers from a pool of available registers to specific data types and to support such dynamic allocation in the processor. It would further be advantageous to enable conversion of values from one data type in one register to another without requiring transfer of the converted value to memory, but permitting the converted value to be transferred directly from one register type to another.